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STA326
2.1 HIGH EFFICIENCY DIGITAL AUDIO SYSTEM
1

FEATURES
Wide supply voltage range (10-36V) 3 Power Output Configurations - 2x30W + 1x60W, 8+4 @ 10% THD - 2x60W, 8 @ 10% THD - 1x120W, 4 @ 10% THD Power SO-36 Package 2.1 Channels of 24-Bit DDX(R) 100dB SNR and Dynamic Range 32kHz to 192kHz Input Sample Rates Digital Gain/Attenuation +48dB to -80dB in 0.5dB steps 4 x 22-bit User Programmable Biquads (EQ) per Channel I2C Control 2-Channel I2S Input Data Interface Individual Channel and Master Gain/ Attenuation Individual Channel and Master Soft and Hard Mute Individual Channel Volume and EQ Bypass Bass/Treble Tone Control Dual Independent Programmable Limiters/ Compressors AutomodesTM - 31 Preset EQ Curves - 15 Preset Crossover Settings - Auto Volume Controlled Loudness - 3 Preset Volume Curves - 2 Preset Anti-Clipping Modes - Preset Nighttime Listening Mode - Preset TV AGC Input and Output Channel Mapping AM Noise Reduction and PWM Frequency Shifting Modes Soft Volume Update and Muting Auto Zero Detect and Invalid Input Detect Muting Over Current and over-temperature protection with programmable recovery Thermal warning indicator with programmable auto output power reduction Selectable De-emphasis
Figure 1. Package
PowerSO36 (Slug up)

Table 1. Order Codes
Part Number STA326 STA32613TR
Package PowerSO36 (Slug up) Tape & Reel

Post-EQ User Programmable Mix with default 2.1 Bass Management settings Variable Max Power Correction for lower fullpower THD 4 Output Routing Configurations Selectable Clock Input Ratio 96kHz Internal Processing Sample Rate, 24 to 28-bit precision QXpander Video Application: 576 fs input mode suporting
2
DESCRIPTION

The STA326 is an integrated solution of digital audio processing, digital amplifier control, and DDXPower Output Stage, thereby creating a high-power single-chip DDX(R) solution comprising of highquality, high-efficiency, all digital amplification. The STA326 can be configured via digital control to operate in several output modes providing up to 2.1 channels of power output to speakers. This device is capable to deliver up to 2x30W + 1x60W in 2.1 mode or 2x60W in stereo mode. The IC can also be configured as a single paralelled full-bridge capable of high-current operation and 1x120W output. Also provided in the STA326 are a full assortment of digital processing features. This includes up to 4 programmable 28-bit biquads (EQ) per channel, and bass/treble tone control. AutomodesTM enable a time-to-market advantage by substantially reducing the amount of software development needed for certain functions. This includes Auto
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Volume loudness, preset volume curves, preset EQ settings, etc. New advanced AM radio inerference reduction modes. The serial audio data input interface accepts all possible formats, including the popular I2S format. Three channels of DDX(R) processing are provided. This high quality conversion from PCM audio to DDX's patented tri-state PWM switching waveform provides over 100dB SNR and dynamic range. Figure 2.
SDA SCL
I 2C System Control LRCKI BICKI SDI_12 OUT1A Audio EQ, Mix, Crossver, Volume, Limiter Processing DDX (R) Processing Quad Half-Bridge Power Stage OUT1B OUT2A OUT2B System Timing PLL
TWARN FAULT EAPD
Serial Data Input, Channel Mapping & Resampling
Power-Down
CLK
Figure 3. Channel Signal Flow Diagram through the Digital Core
I 2S Input Channel Mapping EQ Processing
Crossover Filter
Re-sampling
Mix
Volume Limiter
4X Interp
DDX(R)
DDX Output
2.1 EQ Processing Two channels of input data (re-sampled if necessary) at 96 kHz are provided to the EQ processing block. In this block, upto 4 user-defined Biquads can be appplied to each of the two channels. Pre-scaling, dc-blocking high-pass, de-emphasis, bass, and tone control filters can also be applied based on various configuration parameter settings. The entire EQ block can be bypassed for all channels simulatneously by setting the DSPB bit to '1'. And the CxEQBP bits can be used to bypass the EQ functionality on a per channel basis. Figure below shows the internal signal flow through the EQ block. 2.2 Mix Processing The Post-EQ Mix block takes the two channel outputs from the EQ block and outputs three channels of data. By default, Channels 1 and 2 outputs are essentially pass-through of Channels 1 and 2 inputs coming from the EQ block. An additional channel is created as a result of a sum & mix of the two input channels. See Figure 30. By default, this 3rd channel of data is an equal mix of channel 1 and 2 data. Normally this third channel will be used as the subwoofer in the 2.1 configuration. An additional filtering stage is found after the mix block in order to implement crossover filtering. The crossover filters can be automatically configured from the AutoMode Crossover (XO) bits or these filters can be manually programmed for any type and frequency crossover.
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2.3 Output Mode Configurations Figure 4. Channel Signal Flow through the EQ Block
Re-sampled Input
Pre Scale
High-Pass Filter
BQ#1
BQ#2
BQ#3
BQ#4
DeEmphasis
Bass Filter
T reble Filt er
To Mix
If HPB = 0
4 Biquads User defined if AMEQ = 00 P reset EQ if AMEQ = 01 Auto Loudness if AMEQ = 10
If DEMP = 1
If CxT CB = 0 BT C: Bass Boost /Cut T T C: T reble Boost/Cut
If DSPB = 0 & CxEQB = 0
Figure 5. 2-Channel (Full-bridge) Power, OCFG(1...0) = 00
Half Bridge
OUT1A
Channel 1
Half Bridge
OUT1B OUT2A
Half Bridge
Channel 2
Half Bridge
OUT2B
Figure 6. - 2.1-Channel Power Configuration OCFG(1...0) = 01
Half Bridge
Channel 1
OUT1A
Half Bridge
Channel 2
OUT1B OUT2A
Half Bridge
Channel 3
Half Bridge
OUT2B
Figure 7. 1-Channel Mono-Parallel Configuration, OCFG(1...0) = 11
OUT1A
Half Bridge
Half Bridge
OUT1B
Channel 3
Half Bridge
OUT2A
Half Bridge
OUT2B
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3
Pin Function and Specifications
Figure 8. Pin Connection (Top view)
VCCSign VSS VDD GND BICKI LRCKI SDI VDDA GNDA XTI PLL FILTER RES SDA SCL RESET CONFIG VL VDD REG 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19
D04AU1540
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
N.C. N.C. OUT2B VCC2B N.C. GND2B GND2A VCC2A OUT2A OUT1B VCC1B GND1B GND1A. N.C. VCC1A OUT1A GNDCLEAN GND REG
Table 2. Pin Function
Pin 1, 2, 5, 14 3 4 6 7 8 9 10 11 12 13 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 4/43 Type O I/O I/O I/O I/O O O I/O I/O I/O. I/O O I/O I/O I/O I/O I I I I/O RES I I I/O I/O I I/O I I/O I/O I/O I/O Name N.C. OUT2B VCC2B GND2B GND2A VCC2A OUT2A OUT1B VCC1B GND1B GND1A VCC1A OUT1A GNDCLEAN GNDREG VREG1 VL CONFIG RESET SCL SDA Reserved PLL FILTER XTI GNDA VDDA SDI_12 LRCKI BICKI GND VDD VSS VCCSIGN Description Not Connected Output half bridge 2B Positive supply Negative Supply Negative Supply Positive supply Output half bridge 2A Output half bridge 1B Positive supply Negative Supply Negative Supply Positive supply Output half bridge 1A Logic reference ground Substrate ground Internal +5V regulator voltage Digital Supply 3.3V Configuration pin (mono parallel) Reset IC Serial Clock IC Serial Data This pin must be connected to GND Connection to PLL filter PLL Input Clock Analog Ground Analog Supply 3.3 IS Serial Data Channels 1 & 2 IS Left/Right Clock, IS Serial Clock Digital Ground Digital Supply 3.3V Internal - 5V (Relative to Vcc) Internal signal supply
STA326
Table 3. Absolute Maximum Ratings
Symbol VDD3 VDDA Vi Vo Tstg Tamb Tj VCC VMAX 3.3V Digital Power Supply 3.3V Analog Power Supply Voltage on input pins Voltage on output pins Storage Temperature Ambient Operating Temperature Operating Junction Temperature DC Supply Voltage Maximum voltage on pins 20 Parameter Value -0.5 to 4 -0.5 to 4 -0.5 to (VDD+0.5) -0.5 to (VDD+0.5) -40 to +150 -20 to +85 0 to +150 40 5.5 Unit V V V V C C C V V
Table 4. Thermal Data
Symbol Rthj-case Tj-SD TWARN Th-SD Parameter Thermal resistance Junction to case (thermal pad) Thermal Shut-down Junction Temperature Thermal Warning Temperature Thermal Shut-down Hysteresis 150 130 25 Min Typ Max 2.5 Unit C/W C C C
Table 5. Recommended Dc Operating Conditions
Symbol VDD3 I/O Power Supply Parameter Value 3.0 to 3.6 Unit V
4
Electrical Characteristcs
(VDD3 = 3.3V 0.3V; Tamb = 25C; unless otherwise specified) 4.1 GENERAL INTERFACE ELECTRICAL CHARACTERISTICS
Symbol Iil Iih IOZ Vesd Parameter Low Level Input no pull-up High Level Input no pull-down Tristate output leakage without pullup/down Electrostatic Protection Test Condition Vi = 0V Vi = VDD3 Vi = VDD3 Leakage < 1A 2000 Min. Typ. Max. 1 2 2 Unit A A A V Note 1 1 1 2
Note 1: The leakage currents are generally very small, < 1na. The values given here are maximum after an electrostatic stress on the pin. Note 2: Human Body Model
4.2 DC ELECTRICAL CHARACTERISTICS: 3.3V BUFFERS
Symbol VIL VIH Vhyst Vol Voh Parameter Low Level Input Voltage High Level Input Voltage Schmitt Trigger Hysteresis Low Level Output High Level Output IoI = 2mA Ioh = -2mA VDD -0.15 2.0 0.4 0.15 Test Condition Min. Typ. Max. 0.8 Unit V V V V V
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4.3 POWER ELECTRICAL CHARACTERISTCS (VL = 3.3V; Vcc = 30V; Tamb = 25C unless otherwise specified)
Symbol RdsON Idss gN gP Dt_s td ON td OFF tr tf VCC IVCCPWRDN
Parameter Power Pchannel/Nchannel MOSFET RdsON Power Pchannel/Nchannel leakage Idss Power Nchannel RdsON Matching Low current Dead Time (static) Turn-on delay time Turn-off delay time Rise time Fall time Supply voltage operating voltage Supply Current from Vcc in PWRDN Supply current from Vcc in Tristate Supply current from Vcc in operation (both channel switching) Overcurrent protection threshold (short circuit current limit) Undervoltage protection threshold Output minimum pulse width Output Power (Full-bridge mode) Output Power (Binary half-bridge mode) Mono mode output power Id=1A
Test conditions
Min.
Typ. 200
Max. 270 50
Unit m A % %
Vcc=35V 95 95 10
Power Pchannel RdsON Matching Id=1A Id=1A see test circuit no.1; see fig. 1 Resistive load Resistive load Resistive load Resistive load; as fig. 1
20 100 100 25 25
ns ns ns ns ns V mA mA mA
10 PWRDN = 0 Vcc=30V; Tri-state Input pulse width = 50% Duty; Switching Frequency = 384Khz; No LC filters; 4 22 80
36 3
IVCC-hiz IVCC
Iout-sh VUV tpw-min Po
6 7
A V 150 ns W W W W W W % dB dB % %
No Load THD = 10% RL = 4; VS = 17V RL = 8; VS = 32V THD = 1% RL = 4; VS = 17V RL = 8; VS = 32V THD = 10% RL = 4; VS = 32V Po = 40 Wrms
70 30 60 25 46 60 120 0.07 0.1 99 92 89 87
Po
Po THD+N SNR
Total Harmonic Distortion + Noise Po = 1 Wrms Signal to Noise Ratio Signal to Noise Ratio, Binary Half-Bridge Mode A-Weighted DDX(R) Mode Binary Mode A-Weighted DDX(R) Mode Binary
Efficiency
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5
FUNCTIONAL DESCRIPTION
5.1 PIN DESCRIPTION 5.1.1 OUT1A, 1B, 2A & 2B (Pins 16, 10, 9 & 3) Output Half Bridge PWM Outputs 1A, 1B, 2A & 2B provide the inputs signals to the speaker devices. Half Bridge Power Outputs 1A, 1B, 2A & 2B deliver audio power to the speaker loads. Using DDX stereo configuration mode, outputs 1A (+) and 1B (-) comprise Channel 1 and outputs 2A (+) and 2B (-) comprise Channel 2. Using binary 2.1 channel configuration mode, output 1A is for Channel 1 and output 1B is for Channel 2 and outputs 2A (+) and 2B (-) comprise Channel 3. Using DDX mono-high power output mode (Config connected to VREG1), outputs 1A and 1B are shorted (+) and outputs 2A and 2B are shorted (-) comprising a single BTL output with twice output current capability for Channel 3. 5.1.2 RESET (Pin 22) Driving RESET low sets all outputs low and returns all register settings to their defaults. The reset is asynchronous to the internal clock. 5.1.3 I2C Signals (Pins 23 & 24) The SDA (I2C Data) and SCL (I2C Clock) pins operate per the I2C specification. See Section 4.0. Fastmode (400kB/sec) I2C communication is supported. 5.1.4 GNDA & VDDA: Phase Locked Loop Power (Pins 28-29) The phase locked loop power is applied here. This +3.3V supply must be well bypassed and filtered for noise immunity. The audio performance of the device is critically dependent upon the PLL circuit. 5.1.5 CLK: Master Clock In (Pin 27) This is the master clock in required for the operation of the digital core. The master clock must be an integer multiple of the LR clock frequency. Typically, the master clock frequency is 12.288 MHz (256*Fs) for a 48kHz sample rate, which is the default at power-up. Care must be taken to avoid over-clocking the device i.e provide the device with the nominally required system clock; otherwise, the device may not properly operate or be able to communicate. 5.1.6 FILTER_PLL: PLL Filter (Pin 26) PLL Filter connects to external filter components for PLL loop compensation. Refer to the schematic diagram for the recommended circuit. 5.1.7 BICKI: Bit Clock In (Pin 32) The serial or bit clock input is for framing each data bit. The bit clock frequency is typically 64*Fs, for example using I2S serial format. 5.1.8 SDI_12: Serial Data Input (Pin 30) PCM audio information enters the device here. Six format choices are available including I2S, left- or rightjustified, LSB or MSB first, with word widths of 16, 18, 20 and 24 bits. 5.1.9 CONFIG: Configuration input (Pin 21) The configuration input pin is normally connected to ground. Using the mono-high power BTL configuration requires the CONFIG input pin be shorted to VREG1. 5.1.10 LRCKI: Left/Right Clock In (Pin 31) The Left/Right clock input is for data word framing. The clock frequency will be at the input sample rate Fs. 5.2 AUDIO PERFORMANCE TBD
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6
STA326 I2C BUS SPECIFICATION
The STA326 supports the I2C protocol. This protocol defines any device that sends data on to the bus as a transmitter and any device that reads the data as a receiver. The device that controls the data transfer is known as the master and the other as the slave. The master always starts the transfer and provides the serial clock for synchronization. The STA326 is always a slave device in all of its communications. 6.1 COMMUNICATION PROTOCOL 6.1.1 Data Transition or change Data changes on the SDA line must only occur when the SCL clock is low. SDA transition while the clock is high is used to identify a START or STOP condition. 6.1.2 Start Condition START is identified by a high to low transition of the data bus SDA signal while the clock signal SCL is stable in the high state. A START condition must precede any command for data transfer. 6.1.3 Stop Condition STOP is identified by a low to high transition of the data bus SDA signal while the clock signal SCL is stable in the high state. A STOP condition terminates communication between STA326 and the bus master. 6.1.4 Data Input During the data input the STA326 samples the SDA signal on the rising edge of clock SCL. For correct device operation the SDA signal must be stable during the rising edge of the clock and the data can change only when the SCL line is low. 6.2 DEVICE ADDRESSING To start communication between the master and the STA326, the master must initiate with a start condition. Following this, the master sends 8-bits (MSB first) onto the SDA line corresponding to the device select address and read or write mode. The 7 most significant bits are the device address identifiers, corresponding to the I2C bus definition. In the STA326 the I2C interface uses a device addresse of 0x34 or 0011010x. The 8th bit (LSB) identifies read or write operation, RW. This bit is set to 1 in read mode and 0 for write mode. After a START condition the STA326 identifies the device address on the bus. If a match is found, it acknowledges the identification on the SDA bus during the 9th bit time. The byte following the device identification byte is the internal space address. 6.3 WRITE OPERATION Following the START condition the master sends a device select code with the RW bit set to 0. The STA326 acknowledges this and then the master writes the internal address byte. After receiving the internal byte address the STA326 again responds with an acknowledgement. 6.3.1 Byte Write In the byte write mode the master sends one data byte. This is acknowledged by the STA326. The master then terminates the transfer by generating a STOP condition. 6.3.2 Multi-byte Write The multi-byte write modes can start from any internal address. Sequential data byte writes will be written to sequential addresses within the STA326. The master generating a STOP condition terminates the transfer.
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6.4 READ OPERATION 6.4.1 Current Address Byte Read Following the START condition the master sends a device select code with the RW bit set to 1. The STA326 acknowledges this and then responds by sending one byte of data. The master then terminates the transfer by generating a STOP condition. 6.4.1.1Current Address Multi-byte Read The multi-byte read modes can start from any internal address. Sequential data bytes will be read from sequential addresses within the STA326. The master acknowledges each data byte read and then generates a STOP condition terminating the transfer. 6.4.2 Random Address Byte Read Following the START condition the master sends a device select code with the RW bit set to 0. The STA326 acknowledges this and then the master writes the internal address byte. After receiving, the internal byte address the STA326 again responds with an acknowledgement. The master then initiates another START condition and sends the device select code with the RW bit set to 1. The STA326 acknowledges this and then responds by sending one byte of data. The master then terminates the transfer by generating a STOP condition. 6.4.2.1Random Address Multi-byte Read The multi-byte read modes could start from any internal address. Sequential data bytes will be read from sequential addresses within the STA326. The master acknowledges each data byte read and then generates a STOP condition terminating the transfer. 6.5 Write Mode Sequence Figure 9. I2C Write Procedure
ACK BYTE WRITE START DEV-ADDR SUB-ADDR ACK DATA IN ACK
RW
STOP
ACK MULTIBYTE WRITE START DEV-ADDR SUB-ADDR
ACK DATA IN
ACK DATA IN
ACK
RW
STOP
6.6 Read Mode Sequence Figure 10. I2C Read Procedure
ACK CURRENT ADDRESS READ START NO ACK
DEV-ADDR
DATA
RW ACK ACK SUB-ADDR
STOP ACK DEV-ADDR DATA NO ACK
RANDOM ADDRESS READ START SEQUENTIAL CURRENT READ START
DEV-ADDR
RW RW= ACK HIGH DEV-ADDR DATA
START ACK DATA
RW ACK DATA NO ACK
STOP
STOP ACK ACK SUB-ADDR DEV-ADDR ACK DATA ACK DATA ACK DATA NO ACK
SEQUENTIAL RANDOM READ START
DEV-ADDR
RW
START
RW
STOP
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7
REGISTER DESCRIPTION
Table 6. Register Summary
Address 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x1F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D Name ConfA ConfB ConfC ConfD ConfE ConfF Mmute Mvol C1Vol C2Vol C3Vol Auto1 Auto2 Auto3 C1Cfg C2Cfg C3Cfg Tone L1ar L1atrt L2ar L2atrt Cfaddr2 B1cf1 B1cf2 B1cf3 B2cf1 B2cf2 B2cf3 A1cf1 A1cf2 A1cf3 A2cf1 A2cf2 A2cf3 B0cf1 B0cf2 B0cf3 Cfud MPCC1 MPCC2 RES RES FDRC1 FDRC2 Status D7 FDRB C2IM MME SVE EAPD MV7 C1V7 C2V7 C3V7 AMPS XO3 C1OM1 C2OM1 C3OM1 TTC3 L1A3 L1AT3 L2A3 L2AT3 CFA7 C1B23 C1B15 C1B7 C2B23 C2B15 C2B7 C3B23 C3B15 C3B7 C4B23 C4B15 C4B7 C5B23 C5B15 C5B7 MPCC15 MPCC7 RES RES FDRC15 FDRC7 PLLUL D6 TWAB C1IM CSZ4 ZDE ZCE PWDN MV6 C1V6 C2V6 C3V6 XO2 C1OM0 C2OM0 C3OM0 TTC2 L1A2 L1AT2 L2A2 L2AT2 CFA6 C1B22 C1B14 C1B6 C2B22 C2B14 C2B6 C3B22 C3B14 C3B6 C4B22 C4B14 C4B6 C5B22 C5B14 C5B6 MPCC14 MPCC6 RES RES FDRC14 FDRC6 D5 TWRB DSCKE CSZ3 DRC DCCV ECLE MV5 C1V5 C2V5 C3V5 AMGC1 XO1 C1LS1 C2LS1 C3LS1 TTC1 L1A1 L1AT1 L2A1 L2AT1 CFA5 C1B21 C1B13 C1B5 C2B21 C2B13 C2B5 C3B21 C3B13 C3B5 C4B21 C4B13 C4B5 C5B21 C5B13 C5B5 MPCC13 MPCC5 RES RES FDRC13 FDRC5 D4 IR1 SAIFB CSZ2 BQL PWMS LDTE MV4 C1V4 C2V4 C3V4 AMGC0 XO1 PEQ4 C1LS0 C2LS0 C3LS0 TTC0 L1A0 L1AT0 L2A0 L2AT0 CFA4 C1B20 C1B12 C1B4 C2B20 C2B12 C2B4 C3B20 C3B12 C3B4 C4B20 C4B12 C4B4 C5B20 C5B12 C5B4 MPCC12 MPCC4 RES RES FDRC12 FDRC4 D3 IR0 SAI3 CSZ1 PSL AME BCLE MV3 C1V3 C2V3 C3V3 AMV1 AMAM2 PEQ3 C1BO C2BO C3BO BTC3 L1R3 L1RT3 L2R3 L2RT3 CFA3 C1B19 C1B11 C1B3 C2B19 C2B11 C2B3 C3B19 C3B11 C3B3 C4B19 C4B11 C4B3 C5B19 C5B11 C5B3 MPCC11 MPCC3 RES RES FDRC11 FDRC3 D2 MCS2 SAI2 CSZ0 DSPB RES IDE MV2 C1V2 C2V2 C3V2 AMV0 AMAM1 PEQ2 C1VBP C2VBP C3VBP BTC2 L1R2 L1RT2 L2R2 L2RT2 CFA2 C1B18 C1B10 C1B2 C2B18 C2B10 C2B2 C3B18 C3B10 C3B2 C4B18 C4B10 C4B2 C5B18 C5B10 C5B2 MPCC10 MPCC2 RES RES FDRC10 FDRC2 D1 MCS1 SAI1 OM1 DEMP MPC OCFG1 MV1 C1V1 C2V1 C3V1 AMEQ1 AMAM0 PEQ1 C1EQBP C2EQBP BTC1 L1R1 L1RT1 L2R1 L2RT1 CFA1 C1B17 C1B9 C1B1 C2B17 C2B9 C2B1 C3B17 C3B9 C3B1 C4B17 C4B9 C4B1 C5B17 C5B9 C5B1 WA MPCC9 MPCC1 RES RES FDRC9 FDRC1 FAULT D0 MCS0 SAI0 OM0 HPB MPCV OCFG0 MMute MV0 C1V0 C2V0 C3V0 AMEQ0 AMAME PEQ0 C1TCB C2TCB BTC0 L1R0 L1RT0 L2R0 L2RT0 CFA0 C1B16 C1B8 C1B0 C2B16 C2B8 C2B0 C3B16 C3B8 C3B0 C4B16 C4B8 C4B0 C5B16 C5B8 C5B0 W1 MPCC8 MPCC0 RES RES FDRC8 FDRC0 TWARN
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7.1 CONFIGURATION REGISTER A (Address 00h)
D7 FDRB 0 D6 TWAB 1 D5 TFRB 1 D4 IR1 0 D3 IR0 0 D2 MCS2 0 D1 MCS1 1 D0 MCS0 1
7.1.1
BIT 0 1 2
Master Clock Select
R/W R/W R/W R/W RST 1 1 0 NAME MCS0 MCS1 MCS2 DESCRIPTION Master Clock Select: Selects the ratio between the input I2S sample frequency and the input clock.
The STA326 will support sample rates of 32kHz, 44.1kHz, 48Khz, 88.2kHz, and 96kHz. Therefore the internal clock will be:

32.768Mhz for 32kHz 45.1584Mhz for 44.1khz, 88.2kHz, and 176.4kHz
49.152Mhz for 48kHz, 96kHz, and 192kHz The external clock frequency provided to the XTI pin must be a multiple of the input sample frequency (fs). The correlation between the input clock and the input sample rate is determined by the status of the MCSx bits and the IR (Input Rate) register bits. The MCSx bits determine the PLL factor generating the internal clock and the IR bit determines the oversampling ratio used internally. Table 7. IR and MCS Settings for Input Sample Rate and Clock Rate
Input Sample Rate fs (kHz) 32, 44.1, 48 88.2, 96 176.4, 192 IR 000 768fs 384fs 384fs 001 512fs 256fs 256fs MCS(2..0) 010 384fs 192fs 192fs 011 256fs 128fs 128fs 100 128fs 64fs 64fs 101 576fs x x
00 01 1X
7.1.2
BIT 4...3
Interpolation Ratio Select
R/W R/W RST 00 NAME IR (1...0) DESCRIPTION Interpolation Ratio Select: Selects internal interpolation ratio based on input I2S sample frequency
The STA326 has variable interpolation (re-sampling) settings such that internal processing and DDX output rates remain consistent. The first processing block interpolates by either 2 times or 1 time (passthrough) or provides a down-sample by a factor of 2. The IR bits determine the re-sampling ratio of this interpolation. Table 8. IR bit settings as a function of Input Sample Rate
Input Sample Rate Fs (kHz) 32 44.1 48 88.2 96 176.4 192 IR (1,0) 00 00 00 01 01 10 10 1st Stage Interpolation Ratio 2 times over-sampling 2 times over-sampling 2 times over-sampling Pass-Through Pass-Through Down-sampling by 2 Down-sampling by 2
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7.1.3
BIT 5
Thermal Warning Recovery Bypass
R/W R/W RST 1 NAME TWRB DESCRIPTION Thermal-Warning Recovery Bypass: 0 - Thermal warning Recovery enabled 1 - Thermal warning Recovery disabled
If the Thermal Warning Adjustment is enabled (TWAB=0), then the Thermal Warning Recovery will determine if the adjustment is removed when Thermal Warning is negative. If TWRB=0 and TWAB=0, then when a thermal warning disappears the gain adjustment determined by the Thermal Warning PostScale(default = -3dB) will be removed and the gain will be added back to the system. If TWRB=1 and TWAB=0, then when a thermal warning disappears the Thermal Warning Post-Scale gain adjustment will remain until TWRB is changed to zero or the device is reset. 7.1.4
BIT 6
Thermal Warning Adjustment Bypass
R/W R/W RST 1 NAME TWAB DESCRIPTION Thermal-Warning Adjustment Bypass: 0 - Thermal warning adjustment enabled 1 - Thermal warning adjustment disabled
The on-chip STA326 Power Output block provides feedback to the digital controller using inputs to the Power Control block. The TWARN input is used to indicate a thermal warning condition. When TWARN is asserted (set to 0) for a period greater than 400ms, the power control block will force an adjustment to the modulation limit in an attempt to eliminate the thermal warning condition. Once the thermal warning volume adjustment is applied, whether the gain is reapplied when TWARN is de-asserted is dependent on the TWRB bit. 7.1.5
BIT 7
Fault Detect Recovery Bypass
R/W R/W RST 0 NAME FDRB DESCRIPTION Fault Detector Recovery Bypass: 0 - Fault Detector Recovery enabled 1 - Fault Detector Recovery disabled
The DDX Power block provides feedback to the digital controller using inputs to the Power Control block. The FAULT input is used to signal a fault condition (either over-current or thermal). When FAULT is asserted (set to 0), the power control block will attempt automatic recovery from the fault by asserting the tristate signal in a sequence to reset the fault and retest the fault status. The sequence period can range from 0.1 milliseconds to 1 second as defined by the Fault-Detect Recovery Constant register (FDRC registers 29-2Ah). This sequence is repeated for as long as the fault condition exists. This feature is enabled by default but can be disabled by setting the FDRB control bit to 1. If Fault-Detect Recovery is disabled (not recommended), an output stage FAULT will cause a shut-down condition, which must be reset either by toggling the external reset pin or via a VCC power cycle to the IC. 7.2 CONFIGURATION REGISTER B (Address 01h)
D7 C1IM 1 D6 C1IM 0 D5 DSCKE 0 D4 SAIFB 0 D3 SAI3 0 D2 SAI2 0 D1 SAI1 0 D0 SAI0 0
7.2.1
BIT 3...0
Serial Audio Input Interface Format
R/W R/W RST 0000 NAME SAI (3...0) DESCRIPTION Serial Audio Input Interface Format: Determines the interface format of the input serial digital audio interface.
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7.3 Serial Data Interface The STA326 serial audio input was designed to interface with standard digital audio components and to accept a number of serial data formats. The STA326 always acts as a slave when receiving audio input from standard digital audio components. Serial data for two channels is provided using 3 input pins: left/ right clock LRCKI (pin 33), serial clock BICKI (pin 31), and serial data 1 & 2 SDI12 (pin 32). The SAI register (Configuration Register B - 01h, Bits D3-D0) and the SAIFB register (Configuration Register B - 01h, Bit D4) are used to specify the serial data format. The default serial data format is I2S, MSBFirst. Available formats are shown in Figure 11 and the tables that follow. Figure 11. General Serial Input and Output Formats
IS
LRCLK Left Right
2
SCLK
SDATA
MSB
LSB
MSB
LSB
MSB
Left Justified
LRCLK Left Right
SCLK
SDATA
MSB
LSB
MSB
LSB
MSB
Right Justified
LRCLK Left Right
SCLK
SDATA
MSB
LSB
MSB
LSB
MSB
For example, SAI=1110 and SAIFB=1 would specify Right-Justified 16-bit data, LSB-First. Table 10 below lists the serial audio input formats supported by STA326 as related to BICKI = 32/48/64fs, where the sampling rate fs = 32/44.1/48/88.2/96/176.4/192 kHz. Table 9. First Bit Selection Table
SAIFB 0 1
Note: Serial input and output formats are specified distinctly.
Format MSB-First LSB-First
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Table 10. Supported Serial Audio Input Formats
BICKI 32fs SAI (3...0) 1100 1110 48fs 0100 0100 1000 0100 1100 0001 0101 1001 1101 0010 0110 1010 1110 64fs 0000 0100 1000 0000 1100 0001 0101 1001 1101 0010 0110 1010 1110 SAIFB X X X X X 0 1 X X X X X X X X X X X 0 1 X X X X X X X X Interface Format I2S 15bit Data Left/Right-Justified 16bit Data I2S 23bit Data I2S 20bit Data I2S 18bit Data MSB First I2S 16bit Data LSB First I2S 16bit Data Left-Justified 24bit Data Left-Justified 20bit Data Left-Justified 18bit Data Left-Justified 16bit Data Right-Justified 24bit Data Right-Justified 20bit Data Right-Justified 18bit Data Right-Justified 16bit Data I2S 24bit Data I2S 20bit Data I2S 18bit Data MSB First I2S 16bit Data LSB First I2S 16bit Data Left-Justified 24bit Data Left-Justified 20bit Data Left-Justified 18bit Data Left-Justified 16bit Data Right-Justified 24bit Data Right-Justified 20bit Data Right-Justified 18bit Data Right-Justified 16bit Data
Table 11. Serial Input Data Timing characteristics (Fs = 32 to 192kHz)
BICKI FREQUENCY (slave mode) BICKI pulse width low (T0) (slave mode) BICKI pulse width high (T1) (slave mode) BICKI active to LRCKI edge delay (T2) BICKI active to LRCKI edge delay (T3) SDI valid to BICKI active setup (T4) BICKI active to SDI hold time (T5) 12.5MHz max. 40 ns min. 40 ns min. 20 ns min. 20 ns min. 20 ns min. 20 ns min.
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Figure 12.
T2 T3 T1 T0
LRCKI BICKI
T4
SDI
T5
7.3.1
BIT 5
Delay Serial Clock Enable
R/W R/W RST 0 NAME DSCKE DESCRIPTION Delay Serial Clock Enable: 0 - No serial clock delay 1 - Serial clock delay by 1 core clock cycle to tolerate anomalies in some I2S master devices
7.3.2
BIT 6
Channel Input Mapping
R/W R/W RST 0 NAME C1IM DESCRIPTION 0 - Processing channel 1 receives Left I2S Input 1 - Processing channel 1 receives Right I2S Input 0 - Processing channel 2 receives Left I2S Input 1 - Processing channel 2 receives Right I2S Input
7
R/W
1
C2IM
Each channel received via I2S can be mapped to any internal processing channel via the Channel Input Mapping registers. This allows for flexibility in processing. The default settings of these registers map each I2S input channel to its corresponding processing channel. 7.4 CONFIGURATION REGISTER C (Address 02h)
D7 D6 CSZ4 1 D5 CSZ3 0 D4 CSZ2 0 D3 CSZ1 0 D2 CSZ0 0 D1 OM1 1 D0 OM0 0
7.4.1
BIT 1...0
DDX(R) Power Output Mode
R/W R/W RST 10 NAME OM (1...0) DESCRIPTION DDX Power Output Mode: Selects configuration of DDX(R) output.
The DDX(R) Power Output Mode selects how the DDX(R) output timing is configured. Different power devices can use different output modes. The DDX-2060/2100/2160 recommended use is OM = 10. When OM=11 the CSZ bits determine the size of the DDX(R) compensating pulse.
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Table 12. DDX(R) Output Modes
OM (1,0) 00 01 10 11 Output Stage - Mode Not Used Not Used STA500/505/508 Variable Compensation
7.4.2 DDX(R) Variable Compensating Pulse Size The DDX(R) variable compensating pulse size is intended to adapt to different power stage ICs. Contact Apogee applications for support when deciding this function. 7.4.3
BIT 6...2
DDX(R) Variable Compensating Pulse Size
R/W R/W RST 10000 NAME CSZ (4...0) DESCRIPTION Compensating Pulse Size Select
The DDX(R) variable compensating pulse size is not recommended to be used except in special circumstances . Contact STMicroelectronics applications for support when deciding this function. Table 13. DDX(R) Compensating Pulse
CSZ (4...0) 00000 00001 ... 10000 ... 11111 Compensating Pulse Size 0 Clock period Compensating Pulse Size 1 Clock period Compensating Pulse Size ... 16 Clock period Compensating Pulse Size ... 31 Clock period Compensating Pulse Size
7.5 Configuration Register D (Address 03h)
D7 MME 0 D6 ZDE 0 D5 DRC 0 D4 BQL 0 D3 PSL 0 D2 DSPB 0 D1 DEMP 0 D0 HPB 0
7.5.1
BIT 0
High-Pass Filter Bypass
R/W R/W RST 0 NAME HPB DESCRIPTION High-Pass Filter Bypass Bit. 0 - AC Coupling High Pass Filter Enabled 1 - AC Coupling High Pass Filter Disabled
The STA326 features an internal digital high-pass filter for the purpose of DC Blocking. The purpose of this filter is to prevent DC signals from passing through a DDX(R) amplifier. DC signals can cause speaker damage.
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7.5.2
BIT 1
De-Emphasis
R/W R/W RST 0 NAME DEMP DESCRIPTION De-emphasis: 0 - No De-emphasis 1 - De-emphasis
By setting this bit to HIGH, or one (1), de-emphasis will implemented on all channels. DSPB (DSP Bypass, Bit D2, CFA) bit must be set to 0 for De-emphasis to function. 7.5.3
BIT 2
DSP Bypass
R/W R/W RST 0 NAME DSPB DESCRIPTION DSP Bypass Bit: 0 - Normal Operation 1 - Bypass of EQ and Mixing Functionality
Setting the DSPB bit bypasses all the EQ and Mixing functionality of the STA326 Core. 7.5.4
BIT 3
Post-Scale Link
R/W R/W RST 0 NAME PSL DESCRIPTION Post-Scale Link: 0 - Each Channel uses individual Post-Scale value 1 - Each Channel uses Channel 1 Post-Scale value
Post-Scale functionality is an attenuation placed after the volume control and directly before the conversion to PWM. Post-Scale can also be used to limit the maximum modulation index and therefore the peak current. A setting of 1 in the PSL register will result in the use of the value stored in Channel 1 post-scale for all three internal channels. 7.5.5
BIT 4
Biquad Coefficient Link
R/W R/W RST 0 NAME BQL DESCRIPTION Biquad Link: 0 - Each Channel uses coefficient values 1 - Each Channel uses Channel 1 coefficient values
For ease of use, all channels can use the biquad coefficients loaded into the Channel 1 Coefficient RAM space by setting the BQL bit to 1. Therefore, any EQ updates only have to be performed once. 7.5.6
BIT 5
Dynamic Range Compression/Anti-Clipping Bit
R/W R/W RST 0 NAME DRC DESCRIPTION Dynamic Range Compression/Anti-Clipping 0 - Limiters act in Anti-Clipping Mode 1 - Limiters act in Dynamic Range Compression Mode
Both limiters can be used in one of two ways, anti-clipping or dynamic range compression. When used in anti-clipping mode the limiter threshold values are constant and dependent on the limiter settings. In dynamic range compression mode the limiter threshold values vary with the volume settings allowing a nighttime listening mode that provides a reduction in the dynamic range regardless of the volume level. 7.5.7
BIT 6
Zero-Detect Mute Enable
R/W R/W RST 1 NAME ZDE DESCRIPTION Zero-Detect Mute Enable: Setting of 1 enables the automatic zerodetect mute
Setting the ZDE bit enables the zero-detect automatic mute. When ZDE=1, the zero-detect circuit looks
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at the input data to each processing channel after the channel-mapping block. If any channel receives 2048 consecutive zero value samples (regardless of fs) then that individual channel is muted if this function is enabled. 7.5.8
BIT 7
Sub-Mix Enable
R/W R/W RST 0 NAME SME DESCRIPTION Sub-Mix Enable: 0 - Sub Mix into Left/Right Disabled 1 - Sub Mix into Left/Right Enabled
Setting the SME bit enables a scaled-mix of the content from the Sub channel (i.e. channel 3) into the main Left & Right channels (i.e. channels 1 & 2). The Sub-Mix resides post-volume & gain compression processing. 7.6 CONFIGURATION REGISTER E (ADDRESS 04H)
D7 SVE 0 D6 ZCE 0 D5 RES 0 D4 PWMS 0 D3 AME 0 D2 RES 0 D1 MPC 0 D0 MPCV 0
7.6.1
BIT 0
Max Power Correction Variable
R/W R/W RST 0 NAME MPCV DESCRIPTION Max Power Correction Variable: 0 - Use Standard MPC Coefficient 1 - Use MPCC bits for MPC Coefficient
By enabling MPC and setting MPCV = 1, the max power correction becomes variable. By adjusting the MPCC registers (address 0x27-0x28) it becomes possible to adjust the THD at maximum unclipped power to a lower value for a particular application. 7.6.2 Max Power Correction
R/W R/W RST 1 NAME MPC DESCRIPTION Max Power Correction: 0 - MPC Disabled 1 - MPC Enabled
BIT 7
Setting the MPC bit corrects the STA500/505/508 power device at high power. This mode will lower the THD+N of a full STA500 DDX(R) system at maximum power output and slightly below. 7.6.3
BIT 2
Noise Shaper BandWidth Selection
R/W R/W RST 0 NAME NSBW DESCRIPTION Noise Shaper BandWidth Select 0 - 4th Order Noise Shaper 1 - 3rd Order Noise Shaper
DDXi-2101 provides the ability to the user to select two types of noise-shaper order. This facilitates the user to essentially make the appropriate bandwidth selection for their design thereby achieving optimal noise performance. It is recommended to set NSBW = '1' when the device is initialized via I2C.
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7.6.4
BIT 3
AM Mode Enable
R/W R/W RST 0 NAME AME DESCRIPTION AM Mode Enable: 0 - Normal DDX(R) operation. 1 - AM reduction mode DDX(R) operation.
The STA326 features a DDX(R) processing mode that minimizes the amount of noise generated in the frequency range of AM radio. This mode is intended for use when DDX(R) is operating in a device with an active AM tuner. The SNR of the DDX(R) processing is reduced to ~83dB in this mode, which is still greater than the SNR of AM radio. 7.6.5
BIT 4
PWM Speed Mode
R/W R/W RST 0 NAME PWMS DESCRIPTION PWM Speed Selection: Normal or Odd
Table 14. PWM Output Speed Selections
PWMS (1...0) 0 1 PWM Output Speed Normal Speed (384kHz) All Channels Odd Speed (341.3kHz) All Channels
7.6.6
BIT 6
Zero-Crossing Volume Enable
R/W R/W RST 1 NAME ZCE DESCRIPTION Zero-Crossing Volume Enable: 1 - Volume adjustments will only occur at digital zero-crossings 0 - Volume adjustments will occur immediately
The ZCE bit enables zero-crossing volume adjustments. When volume is adjusted on digital zero-crossings no clicks will be audible. 7.6.7
BIT 7
Soft Volume Update Enable
R/W R/W RST 1 NAME SVE DESCRIPTION Soft Volume Enable: 1 - Volume adjustments will use soft volume 0 - Volume adjustments will occur immediately
The STA326 includes a soft volume algorithm that will step through the intermediate volume values at a predetermined rate when a volume change occurs. By setting SVE=0 this can be bypassed and volume changes will jump from old to new value directly. This feature is only available if individual channel volume bypass bit is set to `0'. 7.7 Configuration Register F (Address 05h)
D7 EAPD 0 D6 PWDN 1 D5 ECLE 0 D4 RES 1 D3 BCLE 1 D2 IDE 1 D1 OCFG1 1 D0 OCFG0 0
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7.7.1
BIT 1...0
Output Configuration Selection
R/W R/W RST 00 NAME OCFG (1...0) DESCRIPTION Output Configuration Selection 00 - 2-channel (Full-bridge) Power, 1-channel DDX is default
Table 15. Output Configuration Selections
OCFG (1...0) 00 Output Power Configuration 2 Channel (Full-Bridge) Power, 1 Channel DDX: 1A/1B 1A/1B 2A/2B 2A/2B 2(Half-Bridge).1(Full-Bridge) On-Board Power: 1A 1A Binary 2A 1B Binary 3A/3B 2A/2B Binary Reserved 1 Channel Mono-Parallel: 3A 1A/1B 3B 2A/2B
01
10 11
7.7.2
BIT 2
Invalid Input Detect Mute Enable
R/W R/W RST 1 NAME IDE DESCRIPTION Invalid Input Detect Auto-Mute Enable: 0 - Disabled 1 - Enabled
Setting the IDE bit enables this function, which looks at the input I2S data and clocking and will automatically mute all outputs if the signals are perceived as invalid. 7.7.3
BIT 5
Binary Clock Loss Detection Enable
R/W R/W RST 1 NAME BCLE DESCRIPTION Binary Output Mode Clock Loss Detection Enable 0 - Disabled 1 - Enabled
Detects loss of input MCLK in binary mode and will output 50% duty cycle to prevent audible artifacts when input clocking is lost. 7.7.4
BIT 7
Auto-EAPD on Clock Loss Enable
R/W R/W RST 0 NAME ECLE Auto EAPD on Clock Loss 0 - Disabled 1 - Enabled DESCRIPTION
When ECLE is active, it issues a power device power down signal (EAPD) on clock loss detection. 7.7.5
BIT 6
Powerdown
R/W R/W RST 1 NAME PWDN DESCRIPTION Software Power Down: 0 - Powerdown mode operation (auto soft-mute enabled) 1 - Normal Operation
If the powerdown bit is set low, a powerdown sequence is initiated resulting in a soft mute of all the channels and PWM outputs are damped.
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7.7.6
BIT 7
External Amplifier Power Down
R/W R/W RST 0 NAME EAPD DESCRIPTION External Amplifier Power Down: 0 - External Power Stage Power Down Active 1 - Normal Operation
EAPD is used to actively power down a connected DDX(R) Power device. This register has to be written to 1 at start-up to enable the DDX(R) power device for normal operation. 7.8 VOLUME CONTROL 7.8.1 Master Controls
7.8.1.1Master Mute Register (Address 06h)
D7 D6 D5 D4 D3 D2 D1 D0 MMUTE 0
7.8.1.2Master Volume Register (Address 07h)
D7 MV7 1 D6 MV6 1 D5 MV5 1 D4 MV4 1 D3 MV3 1 D2 MV2 1 D1 MV1 1 D0 MV0 1
Note : Value of volume derived from MVOL is dependent on AMV AutoMode Volume settings.
7.8.2
Channel Controls
7.8.2.1Channel 1 Volume (Address 08h)
D7 C1V7 0 D6 C1V6 1 D5 C1V5 1 D4 C1V4 0 D3 C1V3 0 D2 C1V2 0 D1 C1V1 0 D0 C1V0 0
7.8.2.2Channel 2 Volume (Address 09h)
D7 C2V7 0 D6 C2V6 1 D5 C2V5 1 D4 C2V4 0 D3 C2V3 0 D2 C2V2 0 D1 C2V1 0 D0 C2V0 0
7.8.2.3Channel 3 Volume (Address 0Ah)
D7 C3V7 0 D6 C3V6 1 D5 C3V5 1 D4 C3V4 0 D3 C3V3 0 D2 C3V2 0 D1 C3V1 0 D0 C3V0 0
7.8.3 Volume Description The volume structure of the STA326 consists of individual volume registers for each of the three channels and a master volume register, and individual channel volume trim registers. The channel volume settings
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are normally used to set the maximum allowable digital gain and to hard-set gain differences between certain channels. These values are normally set at the initialization of the IC and not changed. The individual channel volumes are adjustable in 0.5dB steps from +48dB to -80 dB. The master volume control is normally mapped to the master volume of the system. The values of these two settings are summed to find the actual gain/volume value for any given channel. When set to 1, the Master Mute will mute all channels, whereas the individual channel mutes (CxM) will mute only that channel. Both the Master Mute and the Channel Mutes provide a "soft mute" with the volume ramping down to mute in 4096 samples from the maximum volume setting at the internal processing rate (~96kHz). A "hard mute" can be obtained by commanding a value of all 1's (FFh) to any channel volume register or the master volume register. When volume offsets are provided via the master volume register any channel whose total volume is less than -100dB will be muted. All changes in volume take place at zero-crossings when ZCE = 1 (configuration register E) on a per channel basis as this creates the smoothest possible volume transitions. When ZCE=0, volume updates will occur immediately. The STA326 also features a soft-volume update function that will ramp the volume between intermediate values when the value is updated, when SVE = 1 (configuration register E). This feature can be disabled by setting SVE = 0. Each channel also contains an individual channel volume bypass. If a particular channel has volume bypassed via the CxVBP = 1 register then only the channel volume setting for that particular channel affects the volume setting, the master volume setting will not affect that channel. Also, master soft-mute will not affect the channel if CxVBP = 1. Each channel also contains a channel mute. If CxM = 1 a soft mute is performed on that channel Table 16. Master Volume Offset as a function of MV (7..0).
MV (7..0) 00000000 (00h) 00000001 (01h) 00000010 (02h) ... 01001100 (4Ch) ... 11111110 (FEh) 11111111 (FFh) Volume Offset from Channel Value 0dB -0.5dB -1dB ... -38dB ... -127dB Hard Master Mute
Table 17. Channel Volume as a function of CxV (7..0)
CxV (7..0) 00000000 (00h) 00000001 (01h) 00000010 (02h) ... 01100001 (5Fh) 01100000 (60h) 01011111 (61h) ... 11111110 (FEh) 11111111 (FFh) Volume +48dB +47.5dB +47dB ... +0.5dB 0dB -0.5dB ... -79.5 dB Hard Channel Mute
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7.9 AUTOMODE REGISTERS 7.9.1
D7 AMPS 1
Register - AutoModes EQ, Volume, GC (Address 0Bh)
D6 D5 AMGC1 0 D4 AMGC0 0 D3 AMV1 0 D2 AMV0 0 D1 AMEQ1 0 D0 AMEQ0 0
Table 18. AutoMode EQ
AMEQ (1,0) 00 01 10 11 User Programmable Preset EQ - PEQ bits Auto Volume Controlled Loudness Curve Not used Mode (Biquad 1-4)
By setting AMEQ to any setting other than 00 enables AutoMode EQ. When set, biquads 1-4 are not user programmable. Any coefficient settings for these biquads will be ignored. Also when AutoMode EQ is used the pre-scale value for channels 1-2 becomes hard-set to -18dB. Table 19. AutoMode Volume
AMV (1,0) 00 01 10 11 Mode (MVOL) MVOL 0.5dB 256 Steps (Standard) MVOL Auto Curve 30 Steps MVOL Auto Curve 40 Steps MVOL Auto Curve 50 Steps
Table 20. AutoMode Gain Compression/Limiters
AMGC (1...0) 00 01 10 11 User Programmable GC AC No Clipping AC Limited Clipping (10%) DRC Nighttime Listening Mode Mode
7.9.2
BIT 0
AMPS - AutoMode Auto Prescale
R/W R/W RST 0 NAME AMPS DESCRIPTION AutoMode Pre-Scale 0 - -18dB used for Pre-scale when AMEQ /= 00 1 - User Defined Pre-scale when AMEQ /= 00
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7.9.3
D7 XO3 0
Register - AutoMode AM/Pre-Scale/Bass Management Scale (Address 0Ch)
D6 XO2 0 D5 XO1 0 D4 XO0 0 D3 AMAM2 0 D2 AMAM1 0 D1 AMAM0 0 D0 AMAME 0
7.9.3.1AutoMode AM Switching Enable
BIT 0 R/W R/W RST 0 NAME AMAME DESCRIPTION AutoMode AM Enable 0 - Switching Frequency Determined by PWMS Setting 1 - Switching Frequency Determined by AMAM Settings AM Switching Frequency Setting Default: 000
3...1
R/W
000
AMAM (2...0)
Table 21. AutoMode AM Switching Frequency Selection
AMAM (2..0) 000 001 010 011 100 101 110 48kHz/96kHz Input Fs 0.535MHz - 0.720MHz 0.721MHz - 0.900MHz 0.901MHz - 1.100MHz 1.101MHz - 1.300MHz 1.301MHz - 1.480MHz 1.481MHz - 1.600MHz 1.601MHz - 1.700MHz 44.1kHz/88.2kHz Input Fs 0.535MHz - 0.670Mhz 0.671MHz - 0.800MHz 0.801MHz - 1.000MHz 1.001MHz - 1.180MHz 1.181MHz - 1.340Mhz 1.341MHz - 1.500MHz 1.501MHz - 1.700MHz
When DDX(R) is used concurrently with an AM radio tuner, it is advisable to use the AMAM bits to automatically adjust the output PWM switching rate dependent upon the specific radio frequency that the tuner is receiving. The values used in AMAM are also dependent upon the sample rate determined by the ADC used. 7.9.3.2AutoMode Crossover Setting
BIT 7...4 R/W R/W RST 0 NAME XO (3...0) DESCRIPTION AutoMode Crossover Frequency Selection 000 - User Defined Crossover coefficients are used Otherwise - Preset coefficients for the crossover setting desired
The XO bits are used to either select one of the 15 preset crossover frequency settings or enable the user to implement custom crossover filters. The preset crossover settings signify the crossover frequency selected for the 2nd order low pass and 1st order high pass filters used on the processing channels. If a different crossover frequency, other than those available, is desired, then the user needs to set XO = 000 and design custom high-pass and low-pass filters. These filters should then be written to the device coefficient RAM using the I2C communication. Please refer to section 8.6. Table 22. Crossover Frequency Selection
XO (2..0) 0000 0001 0010 0011 0100 0101 0110 0111 Bass Management - Crossover Frequency User 80 Hz 100 Hz 120 Hz 140 Hz 160 Hz 180 Hz 200 Hz
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Table 22. Crossover Frequency Selection (continued)
XO (2..0) 1000 1001 1010 1011 1100 1101 1110 1111 Bass Management - Crossover Frequency 220 Hz 240 Hz 260 Hz 280 Hz 300 Hz 320 Hz 340 Hz 360 Hz
7.9.4
D7
Register - Preset EQ Settings (Address 0Dh)
D6 D5 D4 PEQ4 0 D3 PEQ3 0 D2 PEQ2 0 D1 PEQ1 0 D0 PEQ0 0
Table 23. Preset EQ Selection
PEQ (3..0) 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 Setting Flat Rock Soft Rock Jazz Classical Dance Pop Soft Hard Party Vocal Hip-Hop Dialog Bass-Boost #1 Bass-Boost #2 Bass-Boost #3 Loudness 1 (least boost) Loudness 2 Loudness 3 Loudness 4 Loudness 5 Loudness 6 Loudness 7 Loudness 8 Loudness 9 Loudness 10 Loudness 11 Loudness 12 Loudness 13 Loudness 14 Loudness 15 Loudness 16 (most boost)
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7.10 Channel Configuration Registers 7.10.1 Channel 1 Configuration (Address 0Eh)
D7 C1OM1 0 D6 C1OM0 0 D5 C1LS1 0 D4 C1LS0 0 D3 C1BO 0 D2 C1VBP 0 D1 C1EQBP 0 D0 C1TCB 0
7.10.2 Channel 2 Configuration (Address 0Fh)
D7 C2OM1 0 D6 C2OM0 0 D5 C2LS1 0 D4 C2LS0 0 D3 C2BO 0 D2 C2VBP 0 D1 C2EQBP 0 D0 C2TCB 0
7.10.3 Channel 3 Configuration (Address 10h)
D7 C3OM1 0 D6 C3OM0 0 D5 C3LS1 0 D4 C3LS0 0 D3 C3BO 0 D2 C3VBP 0 D1 D0
EQ control can be bypassed on a per channel basis. If EQ control is bypassed on a given channel the prescale and all 9 filters (high-pass, biquads, de-emphasis, bass management cross-over, bass, treble in any combination) are bypassed for that channel.
CxEQBP:
- 0 Perform EQ on Channel X - normal operation - 1 Bypass EQ on Channel X Tone control (bass/treble) can be bypassed on a per channel basis. If tone control is bypassed on a given channel the two filters that tone control utilizes are bypassed.
CxTCB:
- 0 Perform Tone Control on Channel x - (default operation) - 1 Bypass Tone Control on Channel x Each channel can be configured to output either the patented DDX PWM data or standart binary PWM encoded data. By setting the CxBO bit to `1', each channel can be individually controlled to be in binary operation mode. Also, there is the capability to map each channel independently onto any of the two limiters available within the STA326 or even not map it to any limiter at all (default mode). Table 24. Channel Limiter Mapping Selection
CxLS (1,0) 00 01 10 Channel Limiter Mapping Channel has limiting disabled Channel is mapped to limiter #1 Channel is mapped to limiter #2
Each PWM Output Channel can receive data from any channel output of the volume block. Which channel a particular PWM output receives is dependent upon that channel's CxOM register bits.
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Table 25. Channel PWM Output Mapping
CxOM (1...0) 00 01 10 11 PWM Output From Channel 1 Channel 2 Channel 3 Not used
7.11 Tone Control (Address 11h)
D7 TTC3 0 D6 TTC2 1 D5 TTC1 1 D4 TTC0 1 D3 BTC3 0 D2 BTC2 1 D1 BTC1 1 D0 BTC0 1
Table 26. Tone Control Boost/Cut Selection
BTC (3...0)/TTC (3...0) 0000 0001 ... 0111 0110 0111 1000 1001 ... 1101 1110 1111 Boost/Cut -12dB -12dB ... -4dB -2dB 0dB +2dB +4dB ... +12dB +12dB +12dB
7.12 DYNAMICS CONTROL 7.12.1 Limiter 1 Attack/Release Threshold (Address 12h)
D7 L1A3 0 D6 L1A2 1 D5 L1A1 1 D4 L1A0 0 D3 L1R3 1 D2 L1R2 0 D1 L1R1 1 D0 L1R0 0
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7.12.2 Limiter 1 Attack/Release Threshold (Address 13h)
D7 L1AT3 0 D6 L1AT2 1 D5 L1AT1 1 D4 L1AT0 0 D3 L1RT3 1 D2 L1RT2 0 D1 L1RT1 0 D0 L1RT0 1
7.12.3 Limiter 2 Attack/Release Rate (Address 14h)
D7 L2A3 0 D6 L2A2 1 D5 L2A1 1 D4 L2A0 0 D3 L2R3 1 D2 L2R2 0 D1 L2R1 1 D0 L2R0 0
7.12.4 Limiter 2 Attack/Release Threshold (Address 15h)
D7 L2AT3 0 D6 L2AT2 1 D5 L2AT1 1 D4 L2AT0 0 D3 L2RT3 1 D2 L2RT2 0 D1 L2RT1 0 D0 L2RT0 1
7.12.5 Dynamics Control Description The STA326 includes 2 independent limiter blocks. The purpose of the limiters is to automatically reduce the dynamic range of a recording to prevent the outputs from clipping in anti-clipping mode, or to actively reduce the dynamic range for a better listening environment (such as a night-time listening mode, which is often needed for DVDs.) The two modes are selected via the DRC bit in Configuration Register D, bit 5 address 0x03. Each channel can be mapped to Limiter1, Limiter2, or not mapped. If a channel is not mapped, that channel will clip normally when 0 dB FS is exceeded. Each limiter will look at the present value of each channel that is mapped to it, select the maximum absolute value of all these channels, perform the limiting algorithm on that value, and then if needed adjust the gain of the mapped channels in unison. The limiter attack thresholds are determined by the LxAT registers. When the Attack Thesehold has been exceeded, the limiter, when active, will automatically start reducing the gain. The rate at which the gain is reduced when the attack threshold is exceeded is dependent upon the attack rate register setting for that limiter. The gain reduction occurs on a peak-detect algorithm. The release of limiter, when the gain is again increased, is dependent on a RMS-detect algorithm. The output of the volume/limiter block is passed through an RMS filter. The output of this filter is compared to the release threshold, determined by the Release Threshold register. When the RMS filter output falls below the release threshold, the gain is increased at a rate dependent upon the Release Rate register. The gain can never be increased past its set value and therefore the release will only occur if the limiter has already reduced the gain. The release threshold value can be used to set what is effectively a minimum dynamic range. This is helpful as over-limiting can reduce the dynamic range to virtually zero and cause program material to sound "lifeless". In AC mode the attack and release thresholds are set relative to full-scale. In DRC mode the attack threshold is set relative to the maximum volume setting of the channels mapped to that limiter and the release threshold is set relative to the maximum volume setting plus the attack threshold.
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Figure 13. - Basic Limiter and Volume Flow Diagram
Limiter
RMS
Gain/Volume
Input Gain Attenuation Saturation
Output
Table 27. Limiter Attack Rate Selection
LxA (3...0) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Attack Rate dB/ms 3.1584 2.7072 2.2560 1.8048 1.3536 0.9024 0.4512 0.2256 0.1504 0.1123 0.0902 0.0752 0.0645 0.0564 0.0501 0.0451 Slow Fast
Table 28. Limiter Release Rate Selection
LxR (3...0) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Release Rate dB/ms 0.5116 0.1370 0.0744 0.0499 0.0360 0.0299 0.0264 0.0208 0.0198 0.0172 0.0147 0.0137 0.0134 0.0117 0.0110 0.0104 Slow Fast
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7.12.6 Anti-Clipping Mode Table 29. Limiter Attack Threshold Selection (AC-Mode)
LxAT (3...0) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 AC (dB relative to FS) -12 -10 -8 -6 -4 -2 0 +2 +3 +4 +5 +6 +7 +8 +9 +10
7.12.7 Dynamic Range Compression Mode Table 31. Limiter Attack Threshold Selection (DRC-Mode).
LxAT (3...0) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 DRC (dB relative to Volume) -31 -29 -27 -25 -23 -21 -19 -17 -16 -15 -14 -13 -12 -10 -7 -4
Table 30. Limiter Release Threshold Selection (AC-Mode).
LxRT (3...0) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 AC (dB relative to FS) - -29dB -20dB -16dB -14dB -12dB -10dB -8dB -7dB -6dB -5dB -4dB -3dB -2dB -1dB -0dB
Table 32. Limiter Release Threshold Selection (DRC-Mode).(
LxRT (3...0) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 DRC (db relative to Volume + LxAT) - -38dB -36dB -33dB -31dB -30dB -28dB -26dB -24dB -22dB -20dB -18dB -15dB -12dB -9dB -6dB
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8
USER PROGRAMMABLE PROCESSING
8.1 EQ - BIQUAD EQUATION The biquads use the equation that follows. This is diagrammed in Figure 14 below. Y[n] = 2(b0/2)X[n] + 2(b1/2)X[n-1] + b2X[n-2] - 2(a1/2)Y[n-1] - a2Y[n-2] = b0X[n] + b1X[n-1] + b2X[n-2] - a1Y[n-1] - a2Y[n-2] where Y[n] represents the output and X[n] represents the input. Multipliers are 28-bit signed fractional multipliers, with coefficient values in the range of 800000h (-1) to 7FFFFFh (0.9999998808). Coefficients stored in the User Defined Coefficient RAM are referenced in the following manner: - CxHy0 = b1/2 - CxHy1 = b2 - CxHy2 = -a1/2 - CxHy3 = -a2 - CxHy4 = b0/2 The x represents the channel and the y the biquad number. For example C3H41 is the b0/2 coefficient in the fourth biquad for channel 3 Figure 14. - Biquad Filter
b0 /2 Z
-1
2
+
Z -1
b1 /2 Z -1
2
+
2
-a1 /2
Z -1
b2
+
-a2
8.2 PRE-SCALE The Pre-Scale block which precedes the first biquad is used for attenuation when filters are designed that boost frequencies above 0dBFS. This is a single 28-bit signed multiplier, with 800000h = -1 and 7FFFFFh = 0.9999998808. By default, all pre-scale factors are set to 7FFFFFh. 8.3 POST-SCALE The STA326 provides one additional multiplication after the last interpolation stage and before the distortion compensation on each channel. This is a 24-bit signed fractional multiplier. The scale factor for this multiplier is loaded into RAM using the same I2C registers as the biquad coefficients and the mix. All channels can use the same settings as channel 1 by setting the post-scale link bit. 8.4 MIX/BASS MANAGEMENT The STA326 provides a post-EQ mixing block per channel. Each channel has 2 mixing coefficients, which are each 24-bit signed fractional multipliers, that correspond to the 2 channels of input to the mixing block. These coefficients are accessible via the User Controlled Coefficient RAM described below. The mix coefficients are expressed as 24-bit signed; fractional numbers in the range +1.0 (8388607) to -1.0 (8388608) are used used to provide three channels of output from two channels of filtered input.
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Table 33. Mix/Bass Management Block Diagram
Channel #1 from EQ
C1MX1
+
Channel #2 from EQ
High-Pass XO Filter
Channel#1 to GC/Vol
C1MX2
C2MX1
+
High-Pass XO Filter
Channel#2 to GC/Vol
C2MX2
C3MX1
+
Low-Pass XO Filter
Channel#3 to GC/Vol
C3MX2
User-defined Mix Coefficients
Crossover Frequency determined by XO setting. User-defined when XO = 000
After a mix is achieved, STA326 also provides the capability to implement crossver filters on all channels corresponding to 2.1 bass management solution. Channels 1-2 use a 1st order high-pass filter and channel 3 uses a 2nd order low-pass filter corresponding to the setting of the XO bits of I2C register 0Ch. If XO = 000, user specified crossover filters are used. By default these coefficients correspond to pass-through. However, the user can write these coefficients in a similar way as the EQ biquads. When user-defined setting is selected, the user can only write 2nd order crossover filters. This output is then passed on to the Volume/Limiter block. 8.5 Calculating 24-Bit Signed Fractional Numbers from a dB Value The pre-scale, mixing, and post-scale functions of the STA326 use 24-bit signed fractional multipliers to attenuate signals. These attenuations can also invert the phase and therefore range in value from -1 to +1. It is possible to calculate the coefficient to utilize for a given negative dB value (attenuation) via the equations below. - Non-Inverting Phase Numbers 0 to +1 : - Coefficient = Round(8388607 * 10^(dB/20)) - Inverting Phase Numbers 0 to -1 : - Coefficient = 16777216 - Round(8388607 * 10^(dB/20)) As can be seen by the preceding equations, the value for positive phase 0dB is 0x7FFFFF and the value for negative phase 0dB is 0x800000.
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8.6 USER DEFINED COEFFICIENT RAM 8.6.1
D7 CFA7 0
Coefficient Address Register 1 (Address 16h)
D6 CFA6 0 D5 CFA5 0 D4 CFA4 0 D3 CFA3 0 D2 CFA2 0 D1 CFA1 0 D0 CFA0 0
8.6.2
D7
Coefficient b1Data Register Bits 23...16 (Address 17h)
D6 C1B22 0 D5 C1B21 0 D4 C1B20 0 D3 C1B19 0 D2 C1B18 0 D1 C1B17 0 D0 C1B16 0
C1B23 0
8.6.3
D7
Coefficient b1Data Register Bits 15...8 (Address 18h)
D6 C1B14 0 D5 C1B13 0 D4 C1B12 0 D3 C1B11 0 D2 C1B10 0 D1 C1B9 0 D0 C1B8 0
C1B15 0
8.6.4
D7
Coefficient b1Data Register Bits 7...0 (Address 19h)
D6 C1B6 0 D5 C1B5 0 D4 C1B4 0 D3 C1B3 0 D2 C1B2 0 D1 C1B1 0 D0 C1B0 0
C1B7 0
8.6.5
D7
Coefficient b2 Data Register Bits 23...16 (Address 1Ah)
D6 C2B22 0 D5 C2B21 0 D4 C2B20 0 D3 C2B19 0 D2 C2B18 0 D1 C2B17 0 D0 C2B16 0
C2B23 0
8.6.6
D7
Coefficient b2 Data Register Bits 15...8 (Address 1Bh)
D6 C2B14 0 D5 C2B13 0 D4 C2B12 0 D3 C2B11 0 D2 C2B10 0 D1 C2B9 0 D0 C2B8 0
C2B15 0
8.6.7
D7
Coefficient b2 Data Register Bits 7...0 (Address 1Ch)
D6 C2B6 0 D5 C2B5 0 D4 C2B4 0 D3 C2B3 0 D2 C2B2 0 D1 C2B1 0 D0 C2B0 0
C2B7 0
8.6.8
D7
Coefficient a1 Data Register Bits 23...16 (Address 1Dh)
D6 C1B22 0 D5 C1B21 0 D4 C1B20 0 D3 C1B19 0 D2 C1B18 0 D1 C1B17 0 D0 C1B16 0
C1B23 0
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8.6.9
D7 C3B15 0
1.1.9Coefficient a1 Data Register Bits 15...8 (Address 1Eh)
D6 C3B14 0 D5 C3B13 0 D4 C3B12 0 D3 C3B11 0 D2 C3B10 0 D1 C3B9 0 D0 C3B8 0
8.6.10 Coefficient a1 Data Register Bits 7...0 (Address 1Fh)
D7 C3B7 0 D6 C3B6 0 D5 C3B5 0 D4 C3B4 0 D3 C3B3 0 D2 C3B2 0 D1 C3B1 0 D0 C3B0 0
8.6.11 Coefficient a2 Data Register Bits 23...16 (Address 20h)
D7 C4B23 0 D6 C4B22 0 D5 C4B21 0 D4 C4B20 0 D3 C4B19 0 D2 C4B18 0 D1 C4B17 0 D0 C4B16 0
8.6.12 Coefficient a2 Data Register Bits 15...8 (Address 21h)
D7 C4B15 0 D6 C4B14 0 D5 C4B13 0 D4 C4B12 0 D3 C4B11 0 D2 C4B10 0 D1 C4B9 0 D0 C4B8 0
8.6.13 Coefficient a2 Data Register Bits 7...0 (Address 22h)
D7 C4B7 0 D6 C4B6 0 D5 C4B5 0 D4 C4B4 0 D3 C4B3 0 D2 C4B2 0 D1 C4B1 0 D0 C4B0 0
8.6.14 Coefficient b0 Data Register Bits 23...16 (Address 23h)
D7 C5B23 0 D6 C5B22 0 D5 C5B21 0 D4 C5B20 0 D3 C5B19 0 D2 C5B18 0 D1 C5B17 0 D0 C5B16 0
8.6.15 Coefficient b0 Data Register Bits 15...8 (Address 24h)
D7 C5B15 0 D6 C5B14 0 D5 C5B13 0 D4 C5B12 0 D3 C5B11 0 D2 C5B10 0 D1 C5B9 0 D0 C5B8 0
8.6.16 Coefficient b0 Data Register Bits 7...0 (Address 25h)
D7 C5B7 0 D6 C5B6 0 D5 C5B5 0 D4 C5B4 0 D3 C5B3 0 D2 C5B2 0 D1 C5B1 0 D0 C5B0 0
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8.6.17 Coefficient Write Control Register (Address 26h)
D7 D6 D5 D4 D3 RA 0 D2 R1 0 D1 WA 0 D0 W1 0
Coefficients for EQ, Mix and Scaling are handled internally in the STA326 via RAM. Access to this RAM is available to the user via an I2C register interface. A collection of I2C registers are dedicated to this function. First register contains the coefficient base address, five sets of three registers store the values of the 24-bit coefficients to be written or that were read, and one contains bits used to control the read or write of the coefficient (s) to RAM. The following are instructions for reading and writing coefficients. 8.7 Reading a coefficient from RAM

write 8-bits of address to I2C register 16h write `1' to bit R1 (D2) of I2C register 26h read top 8-bits of coefficient in I2C address 17h read middle 8-bits of coefficient in I2C address 18h read bottom 8-bits of coefficient in I2C address 19h
8.8 Reading a set of coefficients from RAM

write 8-bits of address to I2C register 16h write `1' to bit RA (D3) of I2C register 26h read top 8-bits of coefficient in I2C address 17h read middle 8-bits of coefficient in I2C address 18h read bottom 8-bits of coefficient in I2C address 19h read top 8-bits of coefficient b2 in I2C address 1Ah read middle 8-bits of coefficient b2 in I2C address 1Bh read bottom 8-bits of coefficient b2 in I2C address 1Ch read top 8-bits of coefficient a1 in I2C address 1Dh read middle 8-bits of coefficient a1 in I2C address 1Eh read bottom 8-bits of coefficient a1 in I2C address 1Fh read top 8-bits of coefficient a2 in I2C address 20h read middle 8-bits of coefficient a2 in I2C address 21h read bottom 8-bits of coefficient a2 in I2C address 22h read top 8-bits of coefficient b0 in I2C address 23h read middle 8-bits of coefficient b0 in I2C address 24h read bottom 8-bits of coefficient b0 in I2C address 25h
8.9 Writing a single coefficient to RAM

write 8-bits of address to I2C register 16h write top 8-bits of coefficient in I2C address 17h write middle 8-bits of coefficient in I2C address 18h write bottom 8-bits of coefficient in I2C address 19h write 1 to W1 bit in I2C address 26h
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8.10 Writing a set of coefficients to RAM

write 8-bits of starting address to I2C register 16h write top 8-bits of coefficient b1 in I2C address 17h write middle 8-bits of coefficient b1 in I2C address 18h write bottom 8-bits of coefficient b1 in I2C address 19h write top 8-bits of coefficient b2 in I2C address 1Ah write middle 8-bits of coefficient b2 in I2C address 1Bh write bottom 8-bits of coefficient b2 in I2C address 1Ch write top 8-bits of coefficient a1 in I2C address 1Dh write middle 8-bits of coefficient a1 in I2C address 1Eh write bottom 8-bits of coefficient a1 in I2C address 1Fh write top 8-bits of coefficient a2 in I2C address 20h write middle 8-bits of coefficient a2 in I2C address 21h write bottom 8-bits of coefficient a2 in I2C address 22h write top 8-bits of coefficient b0 in I2C address 23h write middle 8-bits of coefficient b0 in I2C address 24h write bottom 8-bits of coefficient b0 in I2C address 25h
write 1 to WA bit in I2C address 26h The mechanism for writing a set of coefficients to RAM provides a method of updating the five coefficients corresponding to a given biquad (filter) simultaneously to avoid possible unpleasant acoustic side-effects. When using this technique, the 8-bit address would specify the address of the biquad b1 coefficient (e.g. 0, 5, 10, 15, ..., 45 decimal), and the STA326 will generate the RAM addresses as offsets from this base value to write the complete set of coefficient data.
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Table 34. RAM Block for Biquads, Mixing, and Scaling
Index (Decimal) 0 1 2 3 4 5 ... 19 20 21 ... 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 Index (Hex) 00h 01h 02h 03h 04h 05h ... 13h 14h 15h ... 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh Channel 1 - Pre-Scale Channel 2 - Pre-Scale Channel 1 - Post-Scale Channel 2 - Post-Scale Channel 3 - Post-Scale Thermal Warning - Post Scale Channel 1 - Mix 1 Channel 1 - Mix 2 Channel 2 - Mix 1 Channel 2 - Mix 2 Channel 3 - Mix 1 Channel 3 - Mix 2 UNUSED UNUSED Low-Pass 2nd Order Filter For XO = 000 ... Channel 2 - Biquad 4 High-Pass Order Filter For XO = 000 2nd Channel 1 - Biquad 2 ... Channel 1 - Biquad 4 Channel 2 - Biquad 1 Channel 1 - Biquad 1 Coefficient C1H10 (b1/2) C1H11 (b2) C1H12 (a1/2) C1H13 (a2) C1H14 (b0/2) C1H20 ... C1H44 C2H10 C2H11 ... C2H44 C12H0 (b1/2) C12H1 (b2) C12H2 (a1/2) C12H3 (a2) C12H4 (b0/2) C12L0 (b1/2) C12L1 (b2) C12L2 (a1/2) C12L3 (a2) C12L4 (b0/2) C1PreS C2PreS C1PstS C2PstS C3PstS TWPstS C1MX1 C1MX2 C2MX1 C2MX2 C3MX1 C3MX2 Default 000000h 000000h 000000h 000000h 400000h 000000h ... 400000h 000000h 000000h ... 400000h 000000h 000000h 000000h 000000h 400000h 000000h 000000h 000000h 000000h 400000h 7FFFFFh 7FFFFFh 7FFFFFh 7FFFFFh 7FFFFFh 5A9DF7h 7FFFFFh 000000h 000000h 7FFFFFh 400000h 400000h
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8.11 Variable Max Power Correction (Address 27h-28h): MPCC bits determine the 16 MSBs of the MPC compensation coefficient. This coefficient is used in place of the default coefficient when MPCV = 1. Table 35.
D7 MPCC15 0 MPCC7 1 D6 MPCC14 0 MPCC6 1 D5 MPCC13 1 MPCC5 0 D4 MPCC12 0 MPCC4 0 D3 MPCC11 1 MPCC3 0 D2 MPCC10 1 MPCC2 0 D1 MPCC9 0 MPCC1 0 D0 MPCC8 1 MPCC0 0
8.12 Fault Detect Recovery (Address 2Bh-2Ch): FDRC bits specify the 16-bit Fault Detect Recovery time delay. When FAULT is asserted, the TRISTATE output will be immediately asserted low and held low for the time period specified by this constant. A constant value of 0001h in this register is ~.083ms. The default value of 000C specifies ~.1mSec. Table 36.
D7 FRDC15 0 D6 FDRC14 0 D5 FDRC13 0 D4 FDRC12 0 D3 FDRC11 0 D2 FDRC10 0 D1 FDRC9 0 D0 FDRC8 0
D7 FDRC7 0
D6 FDRC6 0
D5 FDRC5 0
D4 FDRC4 0
D3 FDRC3 1
D2 FDRC2 1
D1 FDRC1 0
D0 FDRC0 0
Figure 15.
OUTY Vcc (3/4)Vcc Low current dead time = MAX(DTr,DTf) (1/2)Vcc (1/4)Vcc +Vcc t Duty cycle = 50%
M58
DTr OUTY
M57
DTf
INY
R 8
+ -
V67 = vdc = Vcc/2
D02AU1448
gnd
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9
SCHEMATIC DIAGRAMS
Table 37. Component Selection Table 1
Load 4 6 8 Inductor 10uH 15uH 22uH Capacitor 1.0uF 470nF 470nF
Table 38. Component Selection Table 2
Load 4 6 8 Inductor 22uH 33uH 47uH Capacitor 680nF 470nF 390nF
Figure 16. Schematic Diagram for 2(Half-bridge).1(Full-bridge)-channel On-board Power.
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Figure 17. Schematic Diagram for 2-channel (Full-bridge) Power.
Figure 18. Schematic Diagram for 1-channel Mono-Parallel Power..
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Figure 19. PowerSO36 Slug Up Mechanical Data & Package Dimensions
DIM. A A2 A4 A5 a1 b c D D1 D2 E E1 E2 E3 E4 e e3 G H h L N s mm TYP. inch TYP.
MIN. 3.25 3.1 0.8 0.030 0.22 0.23 15.8 9.4
MAX. 3.43 3.2 1 -0.040 0.38 0.32 16 9.8
MIN. 0.128 0.122 0.031 0.0011 0.008 0.009 0.622 0.37
MAX. 0.135 0.126 0.039 -0.0015 0.015 0.012 0.630 0.38
OUTLINE AND MECHANICAL DATA
0.2
0.008
1 13.9 10.9 5.8 2.9 0.65 11.05 0 15.5 0.8 0.075 15.9 1.1 1.1 10 8 0 0.61 0.031 14.5 11.1 2.9 6.2 3.2 0.547 0.429 0.228 0.114
0.039 0.57 0.437 0.114 0.244 1.259 0.026 0.435 0.003 0.625 0.043 0.043 10 8
PowerSO36 (SLUG UP)
(1) "D and E1" do not include mold flash or protusions. Mold flash or protusions shall not exceed 0.15mm (0.006") (2) No intrusion allowed inwards the leads.
7183931 D
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Table 39. Revision History
Date July 2005 May 2006 Revision 1 2 First Issue Changed from preliminary data to maturity. Description of Changes
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